Back to Science: The Dynamically Reassignable Instruction Execution Register (DRIER)

Ok, well i have strayed from scientific posts for quite a while now, so i decided to start back up with this!! Now the subject matter of this post may go waaaay over your heads, but i will try to make it understandable. Also understand that im beginning writing this at 1:10AM so...bear with me lol.

Ok, so a while back i had this idea about computer processor architecture. See, the way they are currently built, The internal execution registers are set at a fixed size...say 32 or 64 bit, meaning that they are designed to execue eiher 32 or 64 bit instructions.
Now the problem comes in the fact that as far as i understand, when you have a 64 bit instruction register, if you have a 32 bit instruction going into that 64 bit register, the register must wait for a second 32 bit instruction to come along and fill that register the rest of the way up. This can be thought of like a 16 oz cup. if you try to fill that cup using an 8oz measuring cup, it will take twice as long to fill up. This delay in filling the register causes it to be virtually usless for several clock cycles. (a clock cycle is the time measurement in a computer processor. a 3ghz processor runs at 3 billion cycles per second.) While this may not seem like a long time to us as humans..think of it in the long term. If that 64 bit register had to be filled with two 32 bit instructions, it would take a minimum of four clock cycles to execute. This is because it would require two to fill the register, and then two to execute both instructions. Now compare this to one 64 bit instruction, which only takes a minimum of two clock cycles; one for loading, and one for execution. Thus, using purely 64 bit instructions THEORETICALLY would result in %100 more yeild, meaning, say, that you could encode an mp3 in half the time using purley 64 bit instructions. Now i say theoretically, because this is a HIGHLT idealized situation used to illustrate my point. But i think you get what i am saying. Having a fixed register size causes problems in the fact that it wastes perfectly good clock cycles if (and when) your instruction set size is mixed. Now comes my idea. DRIER. WHAT if one could make a processor in which there were multiple paralell execution registers that were all linked together? Meaning that you could have 16 32 bit registers, arrayed in a way so that they formed two lines each 256 bits long. This would allow for multiple possibilities. a) each register could execute a single 256 bit instruction, b) each could execute 8 32 bit instructions simultaniously, or c) each could execute a mixed combonation of differant instruction lengths. The differance between DRIER and standard execution is the way the register is loaded. In a standard system, the execution register is loaded from the "bottom up" meaning that you have to take two clock cycles to fill a 64 bit register with 32 bit instructions. With DRIER, the pipelines are composed not of one massive 256 bit pipeline, but of 8 32 bit pipelines, each able to load itself in one clock cycle. These regieters can also stach though, meaning that two 32 bit registers can merge to execute one 64 bit instruction. Make sense? i know this is getting VERY technical, but im almost done...and if you have any questions, please ask in the comments!! Anyway, this would allow for massive increases in productivity if such a processing architecture was adopted, because there would be very little waste in processing time. All right, well its now 1:30 and i have successfully exhausted myself...so i hope you at least somewhat enjoyed this..and please ask questions if you understood enough to ask!! lol

DrEw